Semiconductor devices such as Dynamic Random Access Memories (DRAMs), synchronous DRAMs (SDRAMs) or other types of volatile memories generally utilize CMOS semiconductor devices. Power for these devices is provided by a standard voltage supply having a positive voltage V.sub.DD relative to a ground voltage V.sub.ss. As is well known, data bits having either logic high state or logic low state are stored in memory cell locations. The high logic level stored in a memory cell generally corresponds to a voltage equivalent to V.sub.DD while the low logic level corresponds to the ground voltage V.sub.SS.
Specifically in dynamic memories, the data bit is stored in a.capacitor, which is charged or discharged through a memory cell access transistor. Typically, NMOS devices have been used in the memory cell array since they take up a smaller layout area, and are thus better suited for higher integration. Using an NMOS access transistor however, requires providing a voltage higher than V.sub.DD to the gate of the memory cell access transistor in order to fully turn it on and avoid any threshold voltage drop. The requirement for generation of a voltage supply, which is higher than V.sub.DD thus, arises. Various circuits have been devised for generating such high voltages for use in volatile memories. Generally, this boosted supply voltage level is referred to symbolically as V.sub.PP This naming convention traces its origins to nonvolatile memories such as EEPROMs and Flash EPROMs wherein programming voltages are generated for cell programming. Although some similarities exist, the generation of V.sub.PP in volatile memories has different design goals and approaches than generating V.sub.PP in nonvolatile memories.
A conventional prior art circuit for generating a V.sub.PP voltage level from V.sub.DD is described with reference to FIG. 1. The circuit illustrated in FIG. 1 employs a conventional ring oscillator (not shown) to generate a V.sub.DD level oscillating signal OSC.sub.-- PUMP, the output of which is connected to an NMOS capacitor C1 for functioning as a charge pump. A second NMOS device T2, with its source-drain path connected between V.sub.DD and the charge pump capacitor C1 at node 1, is used for pre-charging the capacitor C1. Furthermore, A main driving PMOS pass transistor T3 is connected between the charge pump capacitor C1 at node 1 and a V.sub.PP output.
In operation, the ring oscillator 1 generates an oscillating signal OSC.sub.-- PUMP with a constant period T.sub.osc and an amplitude of the source supply voltage V.sub.DD which is provided to one plate of the charge pumping capacitor C1. The other plate of C1 is cyclically precharged by transistor T2 which in turn also receives a V.sub.DD level oscillating signal OSC.sub.-- PRECHARGE at its gate.
When the oscillating signal OSC.sub.-- PUMP is at the ground voltage V.sub.SS, the voltage across the Cl is V.sub.DD -V.sub.TN, where V.sub.TN is a threshold voltage loss of the NMOS transistor T2. When the oscillator voltage changes from V.sub.SS to V.sub.DD, the voltage at the node 1 will also rise from a voltage V.sub.DD -V.sub.TN to a voltage of approximately 2V.sub.DD -V.sub.TN, due to the capacitive coupling effect of capacitor C1. The voltage is transferred to the output V.sub.PP when the PMOS pass transistor T3 is turned on. The voltage V.sub.PP may be charged into a load capacitor C.sub.L (not shown). The oscillation is continued to maintain the V.sub.PP potential. Optionally, a level detector and regulator may be included to pause the pumping action during periods requiring little power.
A disadvantage of this NMOS precharge, PMOS pass generating circuit is that there is always a threshold voltage V.sub.TN loss at a boost node 1. Thus, when V.sub.DD is low, for example during power-up, or at less than 2V.sub.TN, the circuit will not work.
A cross-coupled charge pump circuit using a two-phase charge pump shown in FIG. 2 has been implemented as an improvement over the circuit of FIG. 1. This circuit is capable of compensating for the threshold voltage loss at the boost node due to the bootstrap action of the precharge devices. However, this circuit still has the disadvantage of having a threshold voltage loss in the diode-type NMOS devices T4 at the output stage.
An alternate to the cross-coupled charge pump configuration of FIG. 2 was proposed in U.S. Pat. No. 5,196,996. The circuit shown in FIG. 3 comprises a clamping circuit, a charge pump circuit and a charge transfer circuit. The clamping circuit is provided with an NMOS capacitor C4 having one of its plates connected to a first precharging oscillating signal OSC.sub.-- PRECHARGE. A diode-type NMOS device T5 is also provided having its gate and drain coupled to a source supply voltage V.sub.DD and its source connected to the gate of an NMOS transistor T6 and the other plate of capacitor C4.
The charge pump circuit is provided with an NMOS capacitor C5 having one of its plates coupled to a second main pump oscillating signal OSC.sub.-- PUMP. The other plate of capacitor C5 and the drain of the NMOS transistor T6 are coupled via a PMOS pass transistor T7 to the output V.sub.PP.
Since the gate of the precharging transistor T6 is cyclically boosted above V.sub.DD by the precharging capacitor C4, a full V.sub.DD is provided to the drain of transistor T6, thus overcoming the threshold voltage loss in the output stage. However, the circuit has the disadvantage in that V.sub.DD must be at least greater than twice the threshold voltage, i.e. V.sub.DD .gtoreq.2V.sub.TN. Thus, although this circuit solves the problem of the V.sub.TN loss in generating V.sub.PP, it still has the problem that for low V.sub.DD, i.e. close to 2V.sub.TN, the circuit will not work. Essentially, if an NMOS precharge circuit is used the low V.sub.DD problem will always be present. The reason why many designs choose to live with this problem is that by using NMOS precharge the greater problem of device latch-up is avoided.
It would therefore be advantageous to develop a high voltage generating circuit which provides the constant V.sub.PP output without any threshold voltage drop and which is capable of operating efficiently at low values of V.sub.DD.